Heretofore, the integration density of the semiconductor device has been increased, more finer and highly multilayered distributing wires for elements have correspondingly been required and, in turn, the steps formed between these distributing wires have increasingly been high. For this reason, the ability of an insulating material to fill up the gap formed between distributing wires and the surface flatness of an element after forming an insulating film have become serious problems. With regard to the tolerance in the flatness, the depth of focus of a resist becomes small for ensuring a desired resolution during the photolithography process and there has been reported that the unevenness of the surface of, for instance, a line-and-space pattern of 0.7 .mu.m should be limited to the level of not less than 200 nm. A chip or wafer must satisfy the foregoing requirement throughout the entire area thereof and therefore, the complete leveling of the chip or wafer throughout the entire area thereof is required according to its literal sense.
To solve these problems, there has presently been known a method for filling up steps on the surface of a substrate to thus level the surface through the formation of an insulating film by the chemical vapor deposition method using ozon and tetraethoxysilane as starting materials (O.sub.3 -TEOS AP-CVD), as disclosed in Japanese Un-Examined Patent Publication (hereinafter referred to as "J. P. KOKAI") No. Sho 61-77695.
The O.sub.3 -TEOS APCVD technique is excellent in the step coverage and can ensure excellent filling up properties, but the insulating film is formed in conformity with distributing wires and therefore, it is impossible to level the surface of a substrate over a wide area thereof. Moreover, the O.sub.3 -TEOS APCVD technique also suffers from a problem such that the rate of deposition observed on a wide flat portion differs from that observed on fine and dense distributing wire patterns and accordingly, it is difficult to flatten the surface of a pattern whose distributing wire density varies depending on the position.
In addition, there has also been known a method which comprises grinding the surface of a thick deposited insulating film by the chemical mechanical polishing (CMP) technique as disclosed in, for instance, L. B. Vines and S. K. Gupta, 1986 IEEE VLSI Multilevel Interconnect Conference, p. 506, Santa Clara, Calif. (1986) or R. Chebi and S. Mittal, 1991 IEEE VLSI Multilevel Interconnect Conference, p. 61, Santa Clara, Calif. (1991) or B. M. Somero, R. P. Chebi, E. U. Travis, H. B. Haver, and W. K. Morrow, 1992 IEEE VLSI Multilevel Interconnect Conf., p. 72, Santa Clara, Calif. (1992). It has been said that the CMP technique permits almost ideal leveling of the surface over a wide area if appropriately establishing the conditions for the CMP technique.
However, grooves present between distributing wires should separately be filled up prior to carrying out CMP. More specifically, the CMP technique must be used in combination with other methods such as the CVD technique to fill up such grooves. Moreover, it has been pointed out that the CMP technique per se suffers from various problems to be solved such as a decrease in the throughput, formation of particles, metal/alkali contamination, uncertainty in the detection of the end point of polishing and an increase in the cost of equipment and accordingly, this technique has not yet been widely used.
If taking notice of only the techniques for filling up the grooves between distributing wires, the high density plasma CVD technique in which a substrate is biased (Biased HPD CVD) has attracted interest recently. S. Matsuo and M. Kiuchi, Jpn. J. Appl. Phys., 22, L210 (1983) or K. Machida and H. Oikawa, J. Vac. Sci. Technol., B4, 818 (1986). This technique is a method comprising depositing an oxide film while anisotropically sputter-etching the surface of a substrate with argon ions, unlike the currently used CVD technique, and the technique makes use of ECR or ICP which can ensure a high plasma ion density as a plasma source.
The HDP technique for forming interlayer insulating films is considered to be an almost satisfactory technique for filling up grooves, but projections are formed on the entire surface of a distributing wire pattern due to insufficient sputter etching and therefore, the leveling of the surface should separately be carried out by, for instance, the CMP technique. Moreover, the problems such as particle-formation and reduction in throughput due to the low deposition rate have not yet been solved.
On the other hand, there has widely been adopted, in the production of semiconductor devices, a method for relieving the unevenness of a substrate by forming an insulating film according to the SPIN ON GLASS (SOG) method as disclosed in, for instance, OYO BUTSURI (Applied Physics), Vol. 57, No. 12 (1988). For instance, a hard film comprising SiO.sub.2 formed by the SOG method has generally been used as an interlayer insulating film for LSI multilevel interconnections.
The term "SOG" means a technique comprising applying a solution containing oligosilanols or oligosilicates to a substrate by a spincoater and then thermally hardening the coated solution to form a hard film of SiO.sub.2, or an insulating film formed by the method, or a coating liquid for forming an insulating film. The SOG coating solution may run into narrow grooves formed between distributing wires and the film thus formed may correspondingly fill up the grooves and simultaneously flow into wide and flat recesses. Therefore, the coating solution also permits leveling of the surface having relatively wide and high steps. The SOG process is performed at a low temperature on the order of about 400.degree. C. and therefore, it can be recomended to use the solution for forming interlayer insulating films after the formation of Al distributing wires which are apt to be easily damaged by heating.
There have conventionally been used, as materials for SOG, an oligosilicate called inorganic SOG represented by the general formula: Si(OR).sub.n (OH).sub.4-n and completely free of organic groups bonded to Si atoms. The inorganic SOG undergoes volume shrinkage at a rate of about 20% during hardening with heating. Accordingly, the resulting film has a poor resistance to crack and the inorganic SOG can be coated in a thickness ranging from only 200 to 300 nm by a single coating operation. An SOG film having a thickness at least equal to the height of distributing wires is required for relieving the steps formed by distributing wires whose cross section has an aspect ratio greater than about 1, but such a thick SOG film cannot be formed because the inorganic SOG may cause cracking. In other words, the inorganic SOG cannot be used for leveling a stepped pattern having a high cross sectional aspect ratio.
To eliminate the foregoing drawbacks associated with the inorganic SOG and to improve the shrink properties, flatness, adhesion and resistance to cracks of a film as well as the etch rate thereof, there has been investigated and developed an oligosiloxane called organic SOG which comprises, in the chemical structure, organic substituents directly bonded to an Si atom, i.e., an organic Si and which is represented by the general formula: R.sub.m Si(OR).sub.n (OH).sub.4-n-m. Methyl group is mainly used as the organic substituent because of its thermal stability, gas-generating properties, resistance to plasma, yield value of the resulting film and flexibility thereof, but other kinds of substituents such as a phenyl group may sometimes be used as the organic substituent. The organic SOG is characterized in that the film thereof has a low shrinkage factor during hardening with heating as compared with the film of the inorganic SOG and therefore, the film has high resistance to cracks. In addition, the rate of etching the film with a CHF.sub.3 -containing etching gas is low and almost comparable to that of the CVD film. Therefore, the organic SOG permits the use of a leveling process by the equal velocity etch back method which comprises applying a thick organic SOG layer on a CVD oxide film formed on a pattern, then hardening the organic SOG layer and etching the hardened SOG layer with a CHF.sub.3 -containing etching gas simultaneously with the CVD film.
However, the hardening of the SOG layer by heating is initiated at about 100.degree. C. and this is accompanied by the volume shrinkage of the SOG layer. Thus, the surface which is once flatened by the application of the organic SOG ultimately has unevenness corresponding to the shape of the surface of a substrate and the flatness of the surface is not improved so much.
Moreover, it has been believed that the range of the area on a substrate which is under the influence of the leveling effect due to the flow of the coating solution is limited to local one and only on the order of 10 .mu.m and thus the thickness of the film on the recesses between wide distributing wires of not less than 10 .mu.m is approximately identical to that of the film on the projected portions, i.e., on the distributing wires. More specifically, the steps formed between resesses and projected portions are not relieved at all from the visual field on the order of not less than 10 .mu.m. As has been discussed above, the thickness of the film formed varies depending on the density of the wiring pattern and therefore, the organic SOG is useless for leveling a wide area comparable to those of chips and wafers.
Moreover, the organic SOG undergoes volume shrinkage on the order of at least about 7% during hardening with heating and may crack due to the contraction stress if a film thereof having a thickness of not less than 500 nm is formed by coating, like the inorganic SOG.
The organic SOG film is inferior in the quality and liable to retain or absorb water. For this reason, various troubles are liable to arise due to the gas generated from the SOG film in the subsequent processes. Moreover, the organic SOG film suffers from various problems such that the apparent dielectric constant thereof increases due to the presence of water, the delay increases due to the interline capacity and thus it is insufficient for use as an insulating film for high speed interconnections.
There has been reported several kinds of SOG's which can eliminate the foregoing drawbacks associated with the organic SOG. One of them is a ladder siloxane oligomer which can be represented by the following structural formula: ##STR1## In other words, a methyl group (or a phenyl group) is bonded to each Si atom and the oligomer has a ladder-like regular structure.
The ladder siloxane oligomer causes melt flow through heating like the crystals because of high structural regularity, but suffers from fatal drawbacks such that it cannot form a thick film because of the high shrinkage factor and poor resistance to cracks and that it is lacking in structurally active hydroxyl groups (Si--OH), poorly adhered to the substrate and is liable to cause peeling.
As another measure, there has been known an inorganic SOG prepared from hydrogensiloxane oligomer or perhydrosilazane oligomer. These novel SOG's have a structure free of organic groups directly bonded to Si atoms and are, instead, characterized by having hydrogen atoms directly bonded to Si atoms. Either of them can be used for forming a thick film since it undergoes expansion through absorption of oxygen present in the atmosphere in a furnace during hardening with heating after coating and drying and accordingly has a low apparent shrinkage factor. However, they suffer from a problem such that the uneven shape of the substrate surface is traced on the films thereof due to the shrinkage during application and drying thereof, like the organic SOG and therefore, they cannot be used for leveling the surface over a wide area. Furthermore, free hydroxyl groups remain in the film even after hardening with heating and this becomes a cause of gas-generation and a high dielectric constant.
There has not yet been developed any material which can solve the problems listed above.
On the other hand, the improvement of characteristic properties of insulating films for semiconductor devices, in particular, interlayer insulating films for the LSI multilevel interconnection requires the analysis of the siloxanes constituting the insulating films.
As methods for analyzing siloxanes included in a variety of materials, there have been known those comprising analyzing a sample as such or siloxanes extracted with an appropriate organic solvent by, for instance, infrared spectrophotometry, nuclear magnetic resonance (NMR) spectroscopy, inductive coupled plasma emission spectroscopic analysis (J. P. KOKAI No. Hei 4-40347). In addition, there has also been known a method which comprises chemically decomposing siloxanes to form decomposition products thereof and detecting and analyzing the products (Japanese Examined Patent Publication (hereinafter referred to as "J. P. KOKOKU") No. Sho 62-8146). However, the purpose of all of these methods is to determine the total amount of Si present in a specific material.
Although several methods for analyzing siloxanes have been known as has been discussed above, there has not yet been established any industrially effective method for determining the proportions of organic substituents present in the organic SOG and, in particular, any industrially useful method for accurately and simply analyzing and evaluating the organic SOG, i.e., siloxanes for forming insulating films while correlating the results with the characteristic properties of insulating films for semiconductor devices, in particular, interlayer insulating films for the LSI multilevel interconnection. Moreover, there have been desired for the development of a coating solution for forming an insulating film which can sufficiently improve the characteristic properties of insulating films for semiconductor devices, in particular, interlayer insulating films for the LSI multilevel interconnection and a method for preparing the same as well as a method for forming an insulating film for semiconductor devices.